T 0759/92 () of 22.4.1994

Summary of Facts and Submissions

I. European patent application No. 88 307 183.9 (publication No. 0 303 396) relating to the blowing of conductive links formed on the surface of solid state circuits was refused by decision of the Examining Division.

II. The Examining Division grounded its decision substantially as follows:

Document

D1: Patent Abstracts of Japan, Volume 8, No. 81 (E-238) [1518], 13 April 1984

pertains to a solid state circuit comprising: a lower interconnect level having a conductive link (2) adapted to being rendered non-conductive by the application of radiant energy thereto; a dielectric layer (4) overlying said lower interconnect level; and upper interconnect level (6a, 6b) overlying said dielectric layer (4) and crossing over said lower interconnect level at crossover locations. In this circuit, however, the thickness of the dielectric layer over the link (2) is the same as anywhere else. Starting from this achievement of prior art, the objective problem underlying the invention as defined by Claim 1 is to make the blowing operation easier and more reliable.

Setting this problem does not require the exercise of inventive talent for it is already known from document

D2: IBM Technical Disclosure Bulletin, Volume 22, No. 5 (October 1979), pages 1971-1972.

It is indeed pointed out in (D3) that the dielectric layer (4, 5) overlying a metal conductor (2) fractures along oblique lines (6) upon application of radiant energy, whereby molten material from said conductor (2) uncontrollably splatters over the surface of the structure. To alleviate this drawback, document (D3) proposes to thin the region (7) of the dielectric layer (4, 5) above the line (2) before cutting the latter by a laser beam (3). Thereby, a controlled blowout of the dielectric material takes place.

Though (D3) remains silent as regards how the thickness of the dielectric layer above the links is to be reduced, it is evident to any person of ordinary skill in the matter that this can be easily achieved by etching said layer through openings in an etch-resistant mask. Therefore, bearing in mind his general technical knowledge, a skilled person combining the teachings of documents (D1) and (D3) would arrive at the claimed invention without having to display any inventive talent. The Applicant's contention that (D3) would be only concerned with a reduction of fracturation of the dielectric layer over the link does not invalidate this conclusion. It neglects indeed the acknowledgement in the present application that the difficulty of blowing the links is closely related to the splattering of molten link material as a result of fracturation of the dielectric layer (13). Likewise, the presence of actually two dielectric layers is not of relevance here, since (D3) makes clear that the essential feature is the thickness reduction.

The Appellant furthermore cited passages of document

D2: Patent Abstracts of Japan, Volume 7, No. 103 (E- 173) [1248], 6 May 1983

to corroborate teachings of (D3) and, with reference to the Claims 5 to 7 as originally filed, document

D4: EP-A-0 089 814.

III. The Applicant lodged an appeal against the decision of the Examining Division.

With its Statement of Grounds of Appeal, the Appellant submitted a set of eighteen claims forming the basis of a new main request. Claim 1 of this set reads:

"A solid state circuit comprising:

a lower interconnect level having a conductive link (12) adapted to being rendered non-conductive by the application of radiant energy thereto; a dielectric layer (13) overlying said lower interconnect level; and upper interconnect level (14) overlying said dielectric layer and crossing over said lower interconnect level at crossover locations (25);

wherein said dielectric layer (13) has a thickness that is chosen so as to minimize to a desired degree the capacitance between the upper and lower interconnect levels, or alternatively obtain a desired degree of planarization, or both;

CHARACTERISED IN THAT an etch-resistant masking layer (15,24) is formed over at least said crossover locations, and the thickness of said dielectric layer over said link in the lower interconnect level is chosen to be sufficiently less than the thickness of said dielectric layer under said etch-resistant masking layer so that the magnitude of the radiant energy required to reliably blow the link is substantially reduced due at least in part to a reduction in the absorption of the radiant energy by the dielectric layer."

Claim 10 is independent and relates to a method of making an integrated circuit. To the independent Claims 1 and 10 are respectively appended Claims 2 to 9 and 11 to 18.

IV. The Appellant requests that the decision of the Examining Division be set aside and that a European patent be granted on the basis of Claims 1 to 18 as filed with its Statement of Grounds of Appeal. Subsidiarily, it requests that a patent be granted on the basis of Claims 10 to 18 of the same set, to be renumbered 1 to 9.

Reasons for the Decision

1. Amendments to Claim 1

In addition to the features recited in the pre- characterising part of Claim 1 as refused by the Examining Division, the pre-characterising part of the new Claim 1 submitted with the Statement of Grounds of Appeal states that the dielectric layer (13) overlying the lower interconnect level "has a thickness that is chosen so as to minimize to a desired degree the capacitance between the upper and lower interconnect levels, or alternatively obtain a desired degree of planarization, or both".

The characterising part of the claim was amended by stating that, as a consequence of the chosen thickness of said dielectric layer (13) over the link in the lower interconnect level, "the magnitude of the radiant energy required to reliably blow the link is substantially reduced due at least in part to a reduction in the absorption of the radiant energy by the dielectric layer".

2. In its Statement of Grounds of Appeal, the Appellant set forth that "a person skilled in the art would assume that, in a solid state circuit according to (D3), the thickness of the interlevel dielectric (4) is chosen to be optimum based on various considerations, such as capacitance and planarization" - see the first paragraph on page 4. No such view, however, was taken in relation with documents (D1, D2 and D4), either in the Statement of Grounds of Appeal or during the proceedings before the Examining Division.

It may thus be accepted that the Appellant considered (D3) to disclose the closest prior art and that, pursuant to Rule 29(1) EPC, it delimited its new Claim 1 with respect to this closest prior art.

3. The drawings of document (D3) show a layer (5) of quartz overlying the upper interconnect level and the interlevel layer (4) which covers the lower interconnect level. They furthermore show that, before blowing a link (2) of the lower interconnect level, a thinned region (7) is provided in the upper layer (5), exclusively - see Figure 2 and related part of the description. Pointing out this fact, the Appellant submitted in its Statement of Grounds of Appeal that, while making a solid state circuit with an interlevel dielectric layer having a thickness that is chosen so as to minimize to a desired degree the capacitance between the upper and lower interconnect levels, or alternatively obtain a desired degree of planarization, or both, a skilled person would not feel the necessity to thin said layer over a link to be blown in the lower interconnect level if no upper dielectric layer overlies said interlevel layer.

4. The Board first observes that the amendment performed in the pre-characterising part of Claim 1 lays a condition on the thickness of the dielectric layer (13), thereby affecting the scope of protection conferred by said claim and, therefore, its substance. The Board furthermore observes that no mention of the additional features inserted in the pre-characterising part of Claim 1 can be found in the claims of the application as originally filed, nor in any document giving account of the proceedings before the Examining Division either.

Therefore, whether the above-mentioned amendment involves, or does not involve, an inventive step, cannot be decided on the basis of arguments put forward in any such document, nor can it be decided on the same basis whether the patent application was, or was not, amended in such a way that it contains subject-matter which extends beyond the content of the application as filed. At least the amendments to the pre-characterising part of Claim 1 the Appellant proposed on appeal thus require a substantial further examination in relation to both the formal and substantive requirements of the EPC. Now, as stated in the earlier Decision T 63/86 (OJ EPO 1988, 224), such further examination should be carried out by the Examining Division as the first instance after the Examining Division has itself exercised its discretion under Rule 86(3) EPC. The reasons for this are discussed fully in paragraph 2 of said earlier decision.

5. In the present case, since the Appellant no longer seeks grant of a patent including Claim 1 with text and subject-matter as rejected by the Examining Division, but has filed a main request containing a substantially amended text for Claim 1 and, for the first time, a second independent claim of a different category, it is clearly appropriate that the case should be remitted to the Examining Division in accordance with Decision T 63/86.

ORDER

For these reasons, it is decided that:

1. The decision under appeal is set aside.

2. The case is remitted to the first instance for further examination of the application having regard to the requests as set out in the Statement of Grounds of Appeal.