| European Case Law Identifier: | ECLI:EP:BA:2007:T063606.20070125 | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Date of decision: | 25 January 2007 | ||||||||
| Case number: | T 0636/06 | ||||||||
| Application number: | 99304915.4 | ||||||||
| IPC class: | H03F 3/45 | ||||||||
| Language of proceedings: | EN | ||||||||
| Distribution: | D | ||||||||
| Download and more information: |
|
||||||||
| Title of application: | A common-mode feedback circuit and method | ||||||||
| Applicant name: | LUCENT TECHNOLOGIES INC. | ||||||||
| Opponent name: | - | ||||||||
| Board: | 3.5.02 | ||||||||
| Headnote: | - | ||||||||
| Relevant legal provisions: |
|
||||||||
| Keywords: | - | ||||||||
| Catchwords: |
- |
||||||||
| Cited decisions: |
|
||||||||
| Citing decisions: |
|
||||||||
Summary of Facts and Submissions
I. The appellant contests the decision of the examining division to refuse European patent application No. 99 304 915.4. The reasons given for the refusal were that the main, first and second auxiliary requests filed with letter dated 7 November 2005 did not meet the requirements of Article 123(2) EPC and Article 84 EPC. The third and fourth auxiliary requests filed with the letter dated 1 December 2005 were not admitted in the proceedings because they were late filed and clearly not allowable.
II. The documents:
D1: US-A-5 578 964,
D2: G. Caiulo and al: "Video CMOS Power Buffer with Extended Linearity", IEEE Journal of Solid-State Circuits, vol. 28, No. 7, July 1993, New York (US), pages 845 to 848, XP000322317, and
D3: EP-A-0 520 751,
considered in the first instance proceedings, remain relevant to the present case.
III. Oral proceedings were held on 25 January 2007. As announced beforehand, the appellant did not attend.
IV. It was noted that the appellant requested that the decision under appeal be set aside and that a patent be granted on the basis of the auxiliary request filed with the letter of 24 January 2007.
V. Claim 1 of the auxiliary request filed with the letter dated 24 January 2007 reads as follows:
"Circuitry having a common-mode feedback circuit (100, 200) comprising:
a first input circuit (102, 110; 202, 210) adapted to convert a first output voltage (-Vout) of a differential amplifier (10) into a first current applied to a current-summing node (122, 222);
a second input circuit (104, 112; 204, 212) adapted to convert a second output voltage (+Vout) of the differential amplifier (10) into a second current applied to the current-summing node;
a reference current generator (116, 118; 216, 218) adapted to generate and apply a reference current directly to the current-summing node comprising:
a current source (116, 218); and
a reference transistor (118, 216) having its base/gate connected to receive a reference voltage (Vref) and its channel connected to the current source and to the current-summing node such that current generated by the current source passing through the channel of the reference transistor is applied to the current-summing node; and
a feedback transistor (120, 214) having its base/gate connected to the reference current generator, the channel of the feedback transistor being connected directly to the current-summing node to apply its channel current to the current-summing node, and the base/gate of the feedback transistor being connected to apply a feedback control voltage (124, 220) to the differential amplifier,
characterized in that:
the base/gate of the feedback transistor is directly connected to the current source."
Claims 2 to 4 are dependent on claim 1.
VI. The appellant submitted in writing that the features introduced into claim 1 addressed the objections raised in the annex to the summons to oral proceedings and the Board's communication of 11 January 2007.
Reasons for the Decision
1. The appeal is admissible.
2. With the letter dated 24 January 2007, the appellant filed sets of claims according to a main request and an auxiliary request. The features of claim 1 of the auxiliary request directly correspond to those of the main request, the difference being that the features of the auxiliary request are presented in a more clearly readable way. According to page 1 of this letter, the applicant "makes clear that their request now is for the application to be returned to the Examining Division with an order to grant a patent on the basis of the Auxiliary Request". Accordingly, it is beyond doubt that the auxiliary request filed with the letter dated 24 January 2007 is the appellant's preferred request.
3. The Board is satisfied that the claims and description according to the preferred request meet the requirements of Article 84 EPC and do not contravene Article 123(2) EPC.
3.1 This applies particularly to the present claim 1 whose features are disclosed in the original claim 1 and at page 2, line 13 to page 3, line 7 and page 5, line 19 to page 6, line 11 of the application as originally filed.
3.2 The description has been adapted to the amended claims and to mention the prior art known from documents D1 and D2.
4. Circuitry having a common-mode feedback circuit whose feedback transistor has its base/gate directly connected to the current source of a reference current generator is not disclosed in any of the cited prior art documents D1 to D3. The subject-matter of current claim 1 thus is considered to be new.
4.1 More specifically, D1, which is the closest prior art among the documents cited by the examining division, discloses circuitry having a common-mode feedback circuit which comprises a reference current generator having a reference transistor M16 and a current source IB2. The current source IB2 however is not directly connected to the feedback transistor M22.
5. Having regard to inventive step, it is noted that the feedback transistors shown in all the cited prior art documents have their base/gate and channel connected together and thus work as diodes. According to claim 1, there is no such connection, because the base/gate of the feedback transistor is directly connected to the current source and the channel of the feedback transistor is directly connected to the current-summing node, which is connected to the current source IB2 through the channel of the reference transistor M16. It is not obvious to reconfigure the circuitry of the prior art so that the base/gate of the feedback transistor could be directly connected to the current source. Accordingly, the documents D1 to D3, taken alone or in combination, would not have led the person skilled in the art to consider the arrangement of the reference current generator and feedback transistor recited in claim 1 of the current request.
6. The Board therefore concludes that the subject-matter of claim 1 is considered to be new and involve an inventive step within the meaning of Articles 54 and 56 EPC. The application as amended meets the requirements of the EPC.
ORDER
For these reasons it is decided that :
1. The decision under appeal is set aside.
2. The case is remitted to the department of the first instance with the order to grant a patent in the following version:
claims: 1 to 4 (auxiliary request) filed with the letter dated 24 January 2007;
description: page 1 filed with the letter of 14 December 2006; page 1a filed with the letter of 4 November 2004; pages 2 to 6 as originally filed; page 7 filed with the letter of 22 January 2007;
drawings: figures 1 and 2 of the published application.
