T 0336/05 (Instruction set architecture/LUCENT) of 23.5.2007

Summary of Facts and Submissions

I. This appeal is against the decision of the examining division to refuse the European patent application No. 98307114.3.

II. The appellants submitted the claims on which the decision under appeal is based on 1 March 2004 after having disapproved of amendments to the application documents introduced by the examining division in a communication pursuant to Rule 51(4) EPC dated 4 September 2002. As requested by the appellants on 7 September 2004, the decision was taken on the file as it was standing on 4 October 2004. It refers to the official communications dated 30 October 2003 and 11 June 2004. In the examining division's view, claim 1 was not clear (Article 84 EPC) since the terms "single two-input accumulate statement", "dual two-input accumulate statement", "three-input accumulate statement", "single product statement" and "dual product statement" had no well-recognized meaning. The word "only" in claim 1 was an unallowable disclaimer since its meaning was "not being 3, 4 etc.". Furthermore, the skilled person would have to exercise inventive activity in order to select a reduced set of commands from the 272 theoretically possible instructions, which implied that claim 1 did not contain all the essential features of the invention. Finally, there was an objection under Rule 27(1)(c) EPC because the description did not disclose the invention as claimed.

III. The notice of appeal was received on 1 December 2004 and the appeal fee was paid the same day. The statement setting out the grounds of appeal was received on 14 February 2005. The appellants requested that the file be considered on the basis of the claims before the examining division and argued that the claims fulfilled all the requirements of Article 84 EPC.

IV. In reply to two communications by the Board, the appellants filed amended application documents on 4 April 2007 and 25 April 2007.

V. Claim 1 as submitted on 25 April 2007 reads:

"A microprocessor including two MAC processors, one MAC processor having a first two-input multiplier (M0) and the other MAC processor having a second two-input multiplier (M1), said microprocessor further including four operand registers xh, xl, yh, and yl, selectively connected as inputs for said first and second multipliers, an input of the first multiplier being cross-connected to the input of the second multiplier, said multipliers having output product registers p0 and p1, said first multiplier being connected to a first adder (A0) and said second multiplier being connected to a second adder (A1), an output of the multiplier of one MAC processor being cross-connected to the input of the adder of the other MAC processor, said adders being connected to an accumulator array (a0.. a7) having a plurality of registers, said first adder (A0) receiving as an input the value in p0 and the value of a register selected from said accumulator array and providing an output to the accumulator array, said second adder (A1) receiving as an input the value in p0, the value in p1, and a data value selected from a register in the accumulator array and providing an output to the accumulator array, said microprocessor being connected to a memory system supporting aligned-double word fetches of data, said microprocessor having a reduced set of architected instructions in which the architected instructions for controlling said multipliers and adders are limited to:

only two single two-input accumulate statements of the form:

aD = aS +/- p0,

where aD and aS indicate destination and source accumulator registers, respectively;

four three-input accumulate statement [sic] of the form

aD = aS +/- p0 +/- p1;

four dual two-input accumulate statements of the form

aD = aS +/- p0 aDP = aSP +/- p1,

where aDP and aSP indicate destination and source accumulator registers, respectively, the

destination registers aD and aDP and the source registers aS and aSP each indicating a predefined

pair of accumulator registers;

only one single product statement of the form

p0=xh*yh; and

only four dual-product statements of the form:

p0=xh*yh p1=xh*yl;

p0=xh*yh p1=xl*yl;

p0=xh*yl p1=xl*yh;

p0=xl*yh p1=xl*yl."

Claim 2 is dependent on claim 1.

VI. The appellants request that the decision under appeal be set aside and a patent be granted on the basis of claims 1 and 2 as submitted with the letter dated 25 April 2007.

Reasons for the Decision

1. Admissibility of the appeal

The appeal complies with the requirements referred to in Rule 65(1) EPC and is therefore admissible.

2. Amendments

The Board is satisfied that the amended claims are properly based on original claims 5 to 7. There is thus no objection under Article 123(2) EPC.

3. Clarity, essential features

3.1 The examining division raised a clarity objection against the terms "single two-input accumulate statement", "dual two-input accumulate statement", "three-input accumulate statement", "single product statement" and "dual product statement" because they were held to have no well-recognized meaning. The Board does not uphold this objection. Whether or not these expressions have a conventional meaning, they are clearly defined in the description and could not possibly lead to misunderstandings.

3.2 The examining division further objected to the use of the term "only" in claim 1 as an unallowable disclaimer. The Board notes that the expression "only two... statements", for example, cannot reasonably be understood in any other way than that exactly two statements have been selected (from a larger group of possible instructions), as explained in the description. Thus, in the present context "only" is not more a disclaimer than "exactly" would have been. Furthermore, it is difficult to see how the intended limitation could be expressed in any other way than has been done without straining the original disclosure.

3.3 Claim 1 has been amended in the appeal proceedings and now clearly defines the essential features of the invention by stating the reduced set of instructions explicitly. The claim is based on previous claim 3. The Board notes that the examining division expressly indicated (cf the communication dated 30 October 2003, point 1.11) that claim 3 contained all essential features.

3.4 Hence, the present claims fulfil the requirements of Article 84 EPC.

4. Novelty, inventive step

4.1 The examining division considered document D1 (EP-A-0 681 236) as the closest prior art (cf communication dated 27 February 2002, point 3), a view from which the Board has no reason to deviate. In the Search Report, D1 was categorized as mere "technological background". The examining division issued a communication under Rule 51(4) EPC with respect to an independent claim having a broader scope than current claim 1. It is therefore justified to assume that the examining division would have held the invention as defined in present claim 1 to be new and involving an inventive step. For this reason it is appropriate for the Board to include the issues of novelty and inventive step in the present appeal proceedings (cf Article 111(1) EPC).

4.2 D1 concerns a microprocessor with cross-connected MAC processors having a multiplier connected to an adder. The adders are connected to an accumulator with multiple registers (see figure 10 and corresponding text of the description). The microprocessor can be controlled by accumulate statements and works on words and half-words. The instruction set is described on p.46 to 54. The only part of D1 to which the examining division has referred is p.54 (cf communication dated 27 February 2002, point 3). On this page a number of multiply and accumulate instructions are shown. The operations are indicated (eg "multiply and accumulate") but without any explanations in the description. There is no mention of a reduced instruction set. The Board cannot see that the mere listing of commands in D1 could convincingly be interpreted in the way that the relatively detailed instruction definitions in claim 1 - such as the selection of four specific dual product statements out of theoretically twelve possibilities - could be regarded as disclosed. Thus, the invention is new (Article 54 EPC).

4.3 The aim of the invention is to implement virtually the entire functionality of a large instruction set (272 instructions) using only 65 commands (cf paragraph [0011] of the description). Considering that D1 does not address the technical problem and does not describe the instructions used but merely lists them, the skilled person would have found no pointers to the invention in this document. Thus, the subject-matter of claim 1 involves an inventive step (Article 56 EPC).

5. The description

The examining division's objection under Rule 27(1)(c) EPC has been overcome by the amendments made to p.4.

ORDER

For these reasons it is decided that:

1. The decision under appeal is set aside.

2. The case is remitted to the department of the first instance with the order to grant a patent in the following version:

Claims:

1,2 filed with letter of 25 April 2007

Description:

pages 1, 4a filed with letter of 4 July 2002

pages 2,3, 5-7 as originally filed

page 4 filed on 4 April 2007 (with letter dated 7 November 2006), and

page 8 filed with letter of 25 April 2007

Drawings:

sheets 1/3 to 3/3 as originally filed.