T 1237/04 () of 19.10.2006

Summary of Facts and Submissions

I. This is an appeal of the applicant against the decision of the examining division to refuse European patent application No. 01 307 699.7.

II. The reason given for the refusal was that the independent claims 1 and 6 of the main and auxiliary request then on file lacked clarity.

III. The following documents of the state of the art have been cited during the procedure before the first instance:

D1: WO-A-99/52216;

D2: EP-A-0 801 501;

D3: US-A-5 594 742; and

D4: "Implementation and Performance of a Turbo/MAP Decoder" by Steven S. Pietrobon, published in 1998 in the International Journal of Satellite Communications, vol. 16, pages 23 to 46.

IV. Oral proceedings before the board took place on 19 October 2006. As announced in a letter of 18 September 2006, the appellant was not represented at the oral proceedings. The board noted that it was apparent from the written procedure on the appeal that the appellant requested the grant of a patent in the following version:

Description

Pages 1 to 3, 5 to 9, 12 to 18, 21 to 31 and 34 to 46 as originally filed,

Pages 4, 4A, 10, 11, 19, 20, 32, 33 and 47 filed with a letter of 4 October 2006.

Claims

No. 1 to 3 filed with the letter of 4 October 2006.

Drawings

Sheets 1 to 38 filed with a letter of 22 January 2002.

V. Claim 1 reads as follows:

"An apparatus (1270) for delaying and ordering path metrics in an input sequence (1275) to form an output sequence of path metrics (1265) in a desired order, said apparatus comprising:

first (1910a3-1910d3) and second (1915a-1915d) banks of corresponding multiplexers, the corresponding multiplexers of the first and second banks each receiving a pair of path metrics at inputs thereof and providing a selected one of said pair of path metrics at an output thereof;

a bank of latches (1910a2-1910d2), each of said latches receiving the output of a corresponding multiplexer of the first bank for delaying provision of said output by a predetermined time period;

a third bank of multiplexers (1910a1-1910h1), each multiplexer of the third bank receiving a corresponding one of the path metrics present at the inputs of the multiplexers of the first and second banks, one half of the multiplexers of said third bank further receiving the output of a corresponding latch of said bank of latches and the other half of the multiplexers of said third bank further receiving the output of a corresponding multiplexer of the second bank of multiplexers; and

a controller (1210, 1920a-1920d, 1925a-1925d) coupled to each of said banks for controlling the multiplexers and latches therein so as to provide an output sequence of path metrics in the desired order at the outputs of the multiplexers of the third bank."

Claims 2 and 3 are dependent on claim 1.

VI. The appellant essentially argued as follows:

The applicant had decided to pursue claims directed to the arrangement depicted in Figure 12 of the application. Support for the claims was to be found in Figure 12 and related discussion beginning on page 30 of the patent application. The claims set out the invention in concrete terms that indicated how the effect, i.e. the presentation of the output sequence of path metrics in a desired order, was to be achieved. The input sequence might be modified (as set forth in claim 1) so that the output sequence provided by the third bank of multiplexers was appropriate to at least one decoding mode when the apparatus operated in a reverse trellis processing mode. One embodiment of a reverse trellis process that modified the input sequence was described in Figures 6A-B and 7A-F and related discussion. For another example, the output sequence provided by the third bank of multiplexers might be selected to be the same as the input sequence (as set forth in claim 2) when the apparatus operated in a transparent forward trellis processing mode.

Reasons for the Decision

1. The appeal is admissible.

2. Amendments

Claim 1 as originally filed concerns an apparatus able to alter an input sequence of path metrics to form a desired output sequence of path metrics. According to claim 1 as filed, the apparatus comprises in particular first, second and third cascaded banks of multiplexers, first and second banks of stores and a controller coupled to each of said banks. Present claim 1 omits the second bank of stores that was specified in claim 1 as originally filed. However, this omission is supported by Figure 12 and related description starting on page 30 of the application as filed, which discloses a reverse address processor 1270 that provides facilities for delaying and ordering path metrics to produce a desired pattern of path metrics, wherein the processor 1270 comprises only one bank of latches or stores 1910a2 to 1910d2. Each of the latches 1910a2 to 1910d2 presents a delayed output as the second input to a corresponding one of the multiplexers 1910a1, 1910c1, 1910e1 and 1910g1 of a third bank of multiplexers 1910a1 to 1910h1, which produce corresponding path metrics 1265a to 1265h. The path metrics 1265a to 1265h are collated and presented as reverse trellis path metrics 1265, the output of the reverse address processor 1270 (see page 31, line 24 to page 32, line 2 of the application as filed). It is furthermore apparent from Figure 12 as filed that half (1910a1, 1910c1, 1910e1, 1910g1) of the multiplexers of the third bank receive the output of a corresponding latch of the bank of latches 1910a2 to 1910d2, whereas the other half (1910b1, 1910d1, 1910f1, 1910h1) of the multiplexers of the third bank receive the output of a corresponding multiplexer of the second bank of multiplexers 1915a to 1915d. Thus, present claim 1 does not contain subject-matter which extends beyond the content of the application as filed.

Present claim 2 corresponds to claim 5 as originally filed whereas the features of present claim 3 can be derived from Figure 12 and a passage of the application as filed from page 30, line 21 to page 31, line 4.

The description of the application has been amended to be consistent with the claims and acknowledge the background art disclosed in document D3.

Thus, the amendments to the application do not contravene Article 123(2) EPC.

3. Clarity

Claim 1 defines an apparatus and indicates that the apparatus is for delaying and ordering path metrics in an input sequence to form an output sequence of path metrics in a desired order. Claim 1 further specifies the features of the apparatus (banks of multiplexers, bank of latches, controller and their interrelations) that are essential to achieve that aim. The board considers therefore that claim 1 is clear in the sense of Article 84 EPC.

Claims 2 and 3 specify further features of the apparatus and, in the view of the board, are also clear.

4. Novelty

The prior art document D3 mentions a circuit 1200 that rearranges the order of input metrics based on a specific control input and is made up of twelve two-state switches (see column 12, lines 13 to 26 and Figures 12 and 13 of D3). The description of the present application indicates that it is known to use double buffering to effect the manipulation of path metrics. The documents D1 to D4 do not disclose an apparatus for ordering and delaying path metrics having the features specified in claim 1. The present application claims a priority date of 18 September 2000 from an application in the US, No. 60/233 369. This priority appears to be validly claimed because the priority application includes a Figure 19 and related description from page 27, line 6 to page 28, line 22 that correspond to Figure 12 and page 30, line 9 to page 32, line 5 of the present application, which describe the claimed subject-matter. The European search report mentions UK patent application GB-A-2 357 938 that was published on 4 July 2001 (which is after the priority date of the present application) and thus is not part of the prior art. The European search report further cites PCT international application WO-A-01/26257, which claims a priority as of 5 October 1999. However, WO-A-01/26257 does not disclose an apparatus having the features specified in claim 1. Thus, the subject-matter of claim 1 is not part of the available state of the art and is therefore considered to be new in the sense of Article 54(1) EPC.

5. Inventive step

It is possible to take either the circuit 1200 of document D3 or the double buffering solutions acknowledged in the description of the present application as a starting point for the examination of inventive step. In both cases, the problem to be solved can be seen in providing a different apparatus for delaying and ordering path metrics in an input sequence to form an output sequence of path metrics in a desired order. None of documents D1 to D4 and WO-A-01/26257 discloses or suggests an apparatus with banks of multiplexers and latches interconnected as specified in claim 1. Therefore, the board takes the view that, having regard to the state of the art, the subject-matter of claim 1 is not obvious to a skilled person. Thus, the subject-matter of claim 1 is considered as involving an inventive step in the sense of Article 56 EPC.

6. The subject-matter of claims 2 and 3, which are dependent on claim 1, is thereby also to be considered as being new and involving an inventive step.

ORDER

For these reasons it is decided that:

1. The decision under appeal is set aside.

2. The case is remitted to the first instance with the order to grant a patent in the following version:

Description

Pages 1 to 3, 5 to 9, 12 to 18, 21 to 31 and 34 to 46 as originally filed,

Pages 4, 4A, 10, 11, 19, 20, 32, 33 and 47 filed with the letter of 4 October 2006.

Claims

No. 1 to 3 filed with the letter of 4 October 2006.

Drawings

Sheets 1 to 38 filed with the letter of 22 January 2002.