T 0051/04 (Recticles/KLA-TENCOR) of 9.5.2006

Summary of Facts and Submissions

I. This appeal is against the decision of the examining division to refuse European patent application No. 99 966 428.7.

II. The following document will be referred to in the present decision:

D1: P. DePesa et al., "Automated critical dimension and registration communication", SPIE Vol. 1604, 1991, pp. 26-33.

III. According to the decision appealed, the invention as defined in claim 1 of the then main and first auxiliary requests was not new over D1, and that of the then second auxiliary request was not inventive.

IV. In the statement of grounds of appeal, dated 20 November 2003, the appellant requested that the decision be set aside and a patent be granted based on amended claims.

V. The Board expressed in a communication the opinion that it was doubtful if the subject-matter of claim 1 involved an inventive step with respect to D1 taken in combination with general knowledge in the field, and also with respect to the prior art acknowledged in the application.

VI. Amended claims according to a main request and an auxiliary request were filed by letters dated 4 April 2006 and 5 May 2006, respectively.

VII. Claim 1 according to the main request (excluding the reference signs) reads:

"1. A method of inspecting a reticle, or an integrated circuit (IC) formed from the reticle, using an inspection system, the reticle defining a circuit layer pattern of the IC, the method comprising:

providing an electronic representation of the circuit layer pattern, the electronic representation having a plurality of regions, and wherein at least one of the plurality of regions is a flagged region, having a flag associated with it, and wherein the flag indicates one of a plurality of different inspection types, and at least one of the plurality of regions is a nonflagged region, not having a flag associated with it, and wherein the plurality of regions of the electronic representation correspond to a plurality of regions of the reticle or the IC;

providing a detected test image of the reticle or the IC;

providing a baseline image containing an expected circuit layer pattern of the test image;

for each of the flagged and nonflagged regions of the electronic representation, the inspection system determining whether a region of the test image corresponds to a flagged region of the electronic representation, and if so then determining the inspection type corresponding to the flag, and

when the region of the test image does correspond to a flagged region of the electronic representation,

comparing the region of the test image to a corresponding region in the baseline image using a first inspection procedure to determine whether the region of the reticle or IC has a defect, wherein the flag is read by the inspection system to select the first inspection procedure based on the inspection type corresponding to the flag; and

when the region of the test image corresponds to a nonflagged region of the electronic representation, comparing the region of the test image to a corresponding region in the baseline image using a second inspection procedure to determine whether the second region of the reticle or IC has a defect, and wherein the procedure used in the first inspection procedure is different to the procedure used in the second inspection procedure."

VIII. Claim 1 of the auxiliary request differs from the main request in that the last feature is amended to read:

"/and wherein/ a first threshold used in the first inspection procedure is different to a second threshold used in the second inspection procedure".

IX. Oral proceedings were held on 9 May 2006. The appellant requested that the decision under appeal be set aside and a patent be granted on the basis of the set of claims according to the main request filed on 4 April 2006 or according to the auxiliary request filed on 5 May 2006.

X. At the end of the oral proceedings the Board announced its decision.

Reasons for the Decision

1. The invention

The invention is a method of inspecting a reticle, or an integrated circuit (IC) formed from the reticle, using an inspection system. As described in the present application (cf pp. 1,2,5-8), a reticle (photomask) is an optical element used during photolithography to define specified regions of a semiconductor wafer for etching, ion implantation, or other fabrication process. A reticle inspection system is used to inspect the reticle for defects that may have occurred during its production. The invention provides mechanisms for flagging critical or noncritical regions of the electronic representation of the IC pattern. A test image of the reticle is compared with a "baseline representation" (which may be generated from the circuit pattern data) such that flagged regions of the test image and of the baseline representation are compared using a first inspection procedure whereas nonflagged regions are compared using a second inspection procedure. The two inspection procedures may differ in various ways. According to the present auxiliary request, in particular, the difference lies in the thresholds used.

2. The prior art

2.1 According to the present application (p. 3), conventional inspection processes involve analyzing and comparing the features of an optical image of the reticle with the corresponding features of a baseline image. Each feature difference is then compared against a single threshold value. If the optical image feature varies from the baseline feature by more than the predetermined threshold, a defect is defined.

2.2 D1 concerns inspection (identifying defects in a design) and metrology (measuring dimensions) in connection with photomasks (reticules). As described in the section "Practical applications" (pp. 30,31), a mask vendor builds a "job deck" (software program for driving the electron beam equipment), the mask is written and processed, and a technician calls up the job deck and instructs the software to locate CD (Critical Dimension) marks which are measured and verified "against the properties defined in the data".

3. Novelty

The closest prior art is in the appellant's and the Board's view the inspection method acknowledged as known in the present application. The invention as defined in claim 1 of the appellant's main request differs from this prior art mainly in the use of flags to indicate regions for which one kind of inspection procedure is to be used, whereas nonflagged regions are inspected using a second kind of inspection method. Since in the prior art a single inspection method is used, the invention is new (Article 54 EPC).

4. Inventive step

4.1 Starting out from the closest prior art, the appellant suggests - and the Board agrees - that the technical problem to be solved was to improve the detection of defects. As explained on pages 3 and 4 of the description of the present application, since conventional inspections analyze all features of a given type of reticle with the same threshold and analysis algorithm, some features are inspected too stringently while others are not inspected stringently enough. Critical features of an integrated circuit typically include gate widths of the semiconductor transistor devices. A gate width on the reticle needs to produce a corresponding gate width on the circuit pattern within a relatively small margin of error in order for the fabricated IC device to function properly. If the threshold is set too high, these critical gate areas are not checked adequately enough. Conversely, other features, such as the widths of the interconnections between gate areas, do not affect the function of the IC as much as the gate area width and, thus, do not need to be inspected as stringently. If the threshold is set too low, too many of these noncritical features may be defined as defects such that the inspection results are difficult to interpret and/or computational resources are overloaded. Thus, conventional inspection systems waste resources.

4.2 In the Board's view, it required no inventive skill to identify the drawbacks mentioned above. It is usual for technical designs to include parts involving different tolerances. A person skilled in the art of semiconductor fabrication knows that some features of an IC design are more critical than others. It may be that in the past only the most critical features have been inspected or the inspection method has not been perfectly suited to all features. But this does not mean that the skilled person was not aware that, ideally, a feature on the reticle or IC should be inspected using the tolerance it itself requires, not what other features of the design might require. He must also have realised that using a single threshold entailed the disadvantages mentioned above. Thus, the Board cannot accept the appellant's argument that (part of) the inventive step resides in the recognition that in this situation something "had to be done". If the skilled person can readily identify a technical disadvantage he will, as a matter of course, try to find a way of overcoming it. The relevant question in the present context is therefore whether the skilled person, in order to solve the above problems, would have provided the representation of the circuit layer pattern with flagged and nonflagged regions associated with different inspection procedures, as specified in claim 1.

4.3 Seeking to improve the known inspection method in such a way that the (relatively coarse) comparison with a single predefined threshold is avoided, the skilled person would realise from the problem itself that some features - or regions - of the reticule should be inspected with a higher threshold (less stringently) and some with a smaller (more stringently). It also follows directly that the respective regions would have to be identified in some way. According to D1, which document is relevant since it concerns the fabrication of reticules and ICs, the reticule data are contained in a job deck (p. 31). The job deck would therefore be the natural place to store region definitions and associated thresholds. This conclusion is supported by D1 explicitly mentioning "properties" defined in the data which are used when verifying certain CD (Critical Dimension) marks. Thus, by consulting D1 the skilled person would understand that data associated with reticule regions are suitably stored in the job deck. This corresponds to the wording of claim 1, which states that flags are "associated" with regions of an electronic representation of the circuit layer pattern.

Claim 1 additionally specifies that the inspection system itself determines whether a region is flagged or not. But this is merely a consequence of the obviously desirable property that the inspection should be automatic.

4.4 The appellant has argued that D1 cannot be combined with the prior art described in the application since it concerns metrology, not inspection. The Board does not deny that the person skilled in the art of IC fabrication may distinguish between these two disciplines. However, even if metrology was the main concern in D1, this does not mean that the skilled person would not consider this document at all in connection with inspection. Not only does D1 at some places refer to "inspection" (see eg pp. 26-29), but it also provides information about IC fabrication technology - for example job deck building - which goes beyond the limits of metrology. The skilled person would not hesitate to consult D1 in order to learn more about how ICs are defined (represented) merely because this document covers other subjects as well.

4.5 For these reasons the subject-matter of claim 1 of the main request does not involve an inventive step (Article 56 EPC).

5. The auxiliary request

Claim 1 of the auxiliary request specifies that the first and second inspection procedures differ as to the thresholds used. It follows from the discussion above that also this subject-matter was obvious (Article 56 EPC).

ORDER

For these reasons it is decided that:

The appeal is dismissed.